1. Technical Field
The invention disclosed and claimed herein generally pertains to a method wherein a Hazard Vector, usefully comprising an R bit and a W bit, is used to enhance throughput of dependent instructions in a microprocessor. More particularly, the invention pertains to a method of the above type wherein an older instruction is issued for execution before the dependent instruction, and the results of the two instructions must be written back in order, that is, the older instruction result must be written back before the dependent instruction result. Even more particularly, the invention pertains to a method of the above type wherein the Hazard Vector bits are used to minimize the time interval between issue of the older instruction for execution and issue of the dependent instruction, while at the same time ensuring that respective instruction results are written back in order.
2. Description of Related Art
In a microprocessor, wherein instructions are sequentially executed, an execution generally concludes by writing back the result of the execution into a register such as a floating point register (FPR). For store instructions, execution concludes by reading data from the register, so that the data can be moved and stored somewhere else. Since the executions occur sequentially in the processor, an instruction may be dependent on an older preceding instruction. This could occur if the older and the dependent instructions are both directed to access the same register. In a dependent relationship, it is very important that the two instructions be written back in order, so that both instructions will be able to access the data they are respectively intended to access. For example, a dependent or younger load instruction, executed to write data into a specified register, cannot be allowed to write to the register before an older store instruction has had a chance to read the register. Otherwise, the store instruction would read data that had been changed from what the store instruction was intended to read.
In order to ensure proper timing in executing the sequential instructions, so that successive instructions will be written back in order, a microprocessor must take into account both write after write (WAW) and read after write (RAW) events. A WAW could occur, for example, between a Floating Point Multiply-Add (FMA) instruction and a younger dependent load instruction, if both instructions had the same destination register. As used herein, FMA refers generically to a mathematical operation such as addition or multiplication. Thus, an FMA instruction produces a numerical or other result that must be written to its destination register. Clearly, the result must be written to the destination before the younger load instruction writes new data to the same destination. A RAW could occur between an FMA instruction and a younger store instruction that were both directed to the same register.
At present, to ensure that sequentially executed instruction are written back in order in a microprocessor, a common approach is to hold a dependent instruction at the issue stage, until the older instruction completes its execution cycle and has thus been written back. However, this approach can lead to a reduction in performance, since no work can be done in regard to the dependent instruction, while it is simply waiting for its execution to begin. Performance could be significantly improved, if a younger dependent instruction could begin execution shortly after the older instruction had begun execution, so that the dependent instruction no longer had to wait until the older instruction completed its execution cycle.